The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Ethernet-enabled devices often include an embedded CPU subsystem for processing packets transmitted or received through an Ethernet interface. Transmit and receive paths of a conventional packet-processing subsystem typically have a simple architecture for communicating packets between an Ethernet interface and a host device. This simple architecture of the transmit and receive paths, however, cannot efficiently communicate management frames associated with system management applications, such as alert standard format (ASF) and desktop and mobile architecture for system hardware (DASH) applications. These packet-processing subsystems often copy these frames to an intermediate memory location before data of the frames is processed and forwarded to another interface of the device, such as a universal serial bus (USB), video, audio, and/or print interface. Copying packets to an intermediate memory location consumes valuable CPU cycles, memory, or time, which can increase communication latency and limit the rate at which the packet-processing subsystem can process packet data. A packet-processing subsystem that is unable to process and forward packet data at a sufficient rate may compromise the performance and usability of applications relying on the packet data.